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EDA Engineer

UST

This is a Full-time position in san jose, CA posted January 3, 2023.



Key Qualifications

• The ideal candidate should possess 5+ years of experience in silicon design as relating to CPU systems, storage controllers, network ASIC and others.

• Extensive understanding of SoC building blocks spanning scheduling, queuing, caching, power management, clock tree, and power domains.

• Demonstrated experience in using AI algorithms to modify silicon design workflows.

• Co-simulation experience of RTL with FW, Matlab / System C models with RTL / FW will be needed.

• Proficiency in C/C++/Python in a Linux development environment is required.

• Familiarity extending UVM verification methodology to open source-based simulations tools will be helpful.

• Experience with open-source tools such as Verilator, ICARUS and KLEE will be an added plus.

• Ability to succinctly summarize complex technical concepts with excellent communication skills are a must.

• Mindset to resolve difficult technical challenges with no visible solutions will be needed.

• Consummate team player with the ability to influence all levels of the organization is desired.

Responsibility :

• Develop, design, and mature new AI methods to accelerate silicon design, verification, and validation workflows

• Conduct initial sandbox development, and work with extended teams to create and execute proof of concept demonstrations

• Construct new workflows by developing, augmenting, and interconnecting open source / commercial tools

• Share knowledge within the team by maintaining high quality documentation and mentoring junior colleagues

Academic Background:

• MS/Ph.D in ECE or EE

• Publications in premier venues like: HOTCHIPS, MICRO, OSDI, QRS, TAPAS, ICFEM, ISSTA etc.

• Being an active contributor to open-source EDA projects will be helpful